CWE-1272
Sensitive Information Uncleared Before Debug/Power State Transition
AI Translation Available
The product performs a power or debug state transition, but it does not clear sensitive information that should no longer be accessible due to changes to information access restrictions.
Status
stable
Abstraction
base
Affected Platforms
Hardware Description Language
Verilog
VHDL
Extended Description
AI Translation
A device or system frequently employs many power and sleep states during its normal operation (e.g., normal power, additional power, low power, hibernate, deep sleep, etc.). A device also may be operating within a debug condition. State transitions can happen from one power or debug state to another. If there is information available in the previous state which should not be available in the next state and is not properly removed before the transition into the next state, sensitive information may leak from the system.
Technical Details
AI Translation
Common Consequences
confidentiality
integrity
availability
access control
accountability
authentication
authorization
non-repudiation
Impacts
read memory
read application data
Detection Methods
manual analysis
Potential Mitigations
Phases:
architecture and design
implementation
Descriptions:
•
During state transitions, information not needed in the next state should be removed before the transition to the next state.
Functional Areas
power