CWE-1261

Improper Handling of Single Event Upsets
AI Translation Available

The hardware logic does not effectively handle when single-event upsets (SEUs) occur.

Status
draft
Abstraction
base

Technology trends such as CMOS-transistor down-sizing, use of new materials, and system-on-chip architectures continue to increase the sensitivity of systems to soft errors. These errors are random, and their causes might be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). These soft errors are not permanent in nature and cause temporary bit flips known as single-event upsets (SEUs). SEUs are induced errors in circuits caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs that cause temporary failures. If these failures occur in security-sensitive modules in a chip, it might compromise the security guarantees of the chip. For instance, these temporary failures could be bit flips that change the privilege of a regular user to root.

Common Consequences

availability access control
Impacts
dos: crash, exit, or restart dos: instability gain privileges or assume identity bypass protection mechanism

Potential Mitigations

Phases:
architecture and design
Descriptions:
• SEUs mostly affect SRAMs. For SRAMs storing security-critical data, implement Error-Correcting-Codes (ECC) and Address Interleaving.
• Implement triple-modular redundancy around security-sensitive modules.